When measuring a distance, if it is too long, or the distant object is something having relatively high surface temperature or something capable of vibrating or moving, the conventional measurement method would not be a good choice and must be replaced by other methods, such as a new range finder using laser or infrared rays. It must be noticed that a time-to-digital converter (TDC) is an important building block for this kind of new range finder. Before the circuit is integrated, emitter-coupled logic elements must be used in the circuit of TDC. If a circuit is as large as a Euro-1(10 cm.times.16 cm), occupying a lot of space in TDC and comsuming over than 5 W power, it is absolutely impossible to meet the requirement of a portable range finder. In order to avoid the shortages as described above, the circuit of TDC will be integrated by an electricity-economized process of complementary metal-oxide semiconductor (CMOS). Although the power consumption of TDC developed by new CMOS process can be greatly reduced to 15 mW, the measurement error of a single-shot is up to 3 nanoseconds (nS). Please refer to FIG. 1 showing the major circuit of the conventional CMOS TDC. Shown in FIG. 1 is a pulse-shrinking circuit consisting of a plurality of pulse-shrinking delay elements, 11 '12 ' . . . ' 1N, in a serial connection. FIG. 2 shows the detailed circuit of the pulse-shrinking delay element provided with a voltage of the power source Vdd. The operating principle is described as follows:
Every pulse-shrinking delay element includes two NOT gates. The maximum conducting current of the first NOT gate is controlled by a bias voltage Vbias of the transistor N3 because the conducting path of the first NOT gate, including two transistors P1 and N1, is serially connected with the transistor N3. The lower the bias voltage Vbias, the lower the conductivity of the transistor N3. However, the smaller the maximum conducting current of the first NOT gate, the weaker the ability for promoting the second NOT gate, including two transistors P2 and N2, to toggle its state. Therefore, the waveform of the pulse between two NOT gates has a gently descending edge so that the width of the valid pulse is shrunk and the width of the output pulse is also shrunk. It means that the degree for the width of the input pulse to be shrunk in passing every shrinking delay element can be easily controlled by adjusting the bias voltage Vbias.
During the period for processing a signal as shown in FIG. 1, the conventional TDC must be calibrated continuously. A stable reference pulse T.sub.ref having a known width is regularly sent to the input end of TDC and the delay-locked loop (DLL) 21 can properly adjust the bias voltage Vbias through its feedback loop so that the width of the input reference pulse can be gradually shrunk through a plurality of the pulse-shrinking delay elements 11 '12 ' . . . ' 1N and be finally vanished in the last one. Therefore, the shrinking range provided by every pulse-shrinking delay element is Tref/N. However, when the conventional TDC receives a request for measuring time, the above-described continuous calibration will be temporarily stopped, at the same time, an unknown pulse signal Tin is sent to the input end of TDC wherein the width of the unknown pulse signal Tin is the length of measure time. If the unknown pulse signal Tin is vanished in the nth pulse-shrinking delay element, the length of the measure time is n.times.Tref/N. Generally, the conventional TDC includes 64 pulse-shrinking delay elements in a serial connection and the width of the reference pulse for calibration is 50 nanoseconds, and hence the conventional TDC has a resolution of 50/64=0.78 nS, that is, the width of the least significant bit (LSB). Although the conventional TDC as described above can meet the requirement of a portable TDC with low power comsumption and high accuracy, there are some defects described as follows:
(1) The circuit must be continuously calibrated to ensure that the reference pulse is exactly vanished in the last pulse-shrinking delay element, and hence the logic gate of the pulse-shrinking delay element must be always in switching operation. This is the major cause of power consumption in the conventional TDC.
(2) Because the pulse-shrinking circuit has a plurality of the pulse-shrinking delay elements in a serial connection which will occupy a relatively long length or large area in the wafer, the mismatch among pulse-shrinking delay elements become so worse that more measurement errors may be generated.
(3) In the serially connected circuit of TDC, the number of the pulse-shrinking delay elements must be doubled for increasing an output bit, and the resultant too-long circuit structure needs to be folded into several segments. Unfortunately, the inter-segment wiring is relatively longer than that between pulse-shrinking delay elements, and hence the mismatch among pulse-shrinking delay elements gets worse. This is why the maximum number of output bits of the conventional TDC is limited to 6 or 7 bits.
(4) As shown in FIG. 2, if the width of the unknown pulse signal is so narrow that the voltage V.sub.mid between two NOT gates is unable to be switched to a level below the transtion voltage of the second NOT gate in time, there is no pulse output. The degree of pulse-shrinking in the latter pulse-shrinking delay elements, especially in the last one, is much bigger than that of the front pulse-shrinking delay elements. This phenomenon will also contribute measurement errors.